1. Field of the Invention
The present invention relates to implementing a processor core that allows for conditional execution using a processor flag. In one example, the present invention relates to methods and apparatus for efficiently implementing a single overloaded flag that does not require additional register-memory bandwidth.
2. Description of Related Art
Conventional processors support a variety of instructions sets. The instruction sets include mechanisms for handling conditional execution. Conditional execution allows a processor to determine whether to execute a particular instruction or instruction sequence based on the result or modification of a prior instruction. Assembly language support for conditional execution includes branch instructions and condition codes or flags. High level programming language analogues include if then statements and case statements.
Typical mechanisms for handling conditional instruction execution include the use of fixed semantic flags and comparison tests on registers values. However, there are substantial drawbacks associated with conventional conditional execution mechanisms. In some instances, extra registers or a large number of reserved bit sequences are needed to implement typical conditional execution handling.
Consequently, it is desirable to provide improved methods and apparatus for handling conditional execution.